1. Field of the Invention
The present invention relates to a method of and an apparatus for forming an interconnection or conductive path in an electronic device such as a semiconductor device, for example.
2. Description of the Related Art
To meet requirements for smaller sizes and higher packing densities, electronic devices including integrated semiconductor circuits such as a VLSI circuit, a ULSI circuit, or the like incorporate a multilayer interconnection structure including interconnections and electrodes (hereinafter collectively referred to as "interconnections") with inter-insulating layers disposed therebetween. Efforts are being made to increase the density of and reduce the pattern of interconnections in electronic devices to meet demands for electronic devices of much smaller sizes and higher packing densities.
Interconnections on an upper surface of inter-insulating layer are connected, by way of ohmic contact, through connecting holes such as contact holes or via holes defined in the inter-insulating layer to other interconnections or semiconductor regions (hereinafter referred to as "contact regions") such as impurity-diffused regions of Si semiconductors beneath the inter-insulating layer. The connecting holes are also required to be smaller in diameter.
It is necessary that the inter-insulating layers have a certain thickness in order to provide a desired level of electric reliability and avoid the problem of parasitic capacitance. Consequently, the aspect ratio (depth/diameter) of the connecting holes is relatively large.
Metal plugs may be embedded in connecting holes of large aspect ratios for connection to an upper interconnection layer. To form such metal plugs, blanket tungsten (Blk-W) is deposited by way of chemical vapor deposition (CVD).
To hold a layer of blanket tungsten in intimate contact with a lower layer, a barrier metal layer of Ti is employed as a base layer beneath the upper interconnection layer (see, for example, Shingaku Gihou SMD91-133, pages 19.about.24).
One conventional process of forming such an interconnection structure is illustrated in FIGS. 1A, 1B, and 1C of the accompanying drawings.
In FIGS. 1A, 1B, and 1C, an interconnection will be connected to a semiconductor region 2 of a substrate 1 such as a semiconductor substrate through a connecting hole 4 defined in an inter-insulating layer 3 deposited on the substrate 1, as follows: First, as shown in FIG. 1A, a barrier metal layer 5 of Ti, which is of a multilayer structure composed of a lower barrier metal layer 5A of Ti and an upper barrier metal layer 5B of TiN, is deposited on the inter-insulating layer 3 including the connecting hole 4.
Then, an interconnection material layer 6 of blanket tungsten is deposited on the barrier metal layer 5 so as to fill the recess that has been produced therein by the connecting hole 4.
A thermally oxidized device-separating thick insulating layer 7. i.e., LOCOS, is formed on the substrate 1. A channel-stop region 8 of a high impurity concentration is disposed on the semiconductor surface beneath the thick insulating layer 7.
Then, anisotropic dry etching is effected on the interconnection material layer 6 and the barrier metal layer 5 using a fluorine gas for thereby removing a flat portion of the interconnection material layer 6 except its portion within the connecting hole 4, by way of etchback, as shown in FIG. 1B. Thus, an interconnection contact is formed as a metal plug that is filled in the connecting hole 4 and composed primarily of the interconnection material layer 6 of Blk-W.
Upon anisotropic dry etching using a fluorine gas as of SF.sub.6 or CF.sub.4, for example, the etchback on the interconnection material layer 6 of Blk-W progresses until the lower Ti barrier metal layer 5 is exposed. Thereafter, the etchback on the interconnection material layer 6 of Blk-W ceases. Since only etching of the barrier metal layer 5 subsequently goes on and results in a certain degree of overetching, the interconnection material layer 6 of Blk-W projects beyond the other portions, as shown in FIG. 1C. If an interconnection pattern of Al or the like is formed on the projecting interconnection material layer 6, it may possibly be broken or otherwise damaged thereby.
It has been found out that such a phenomenon is caused for the following reason: At the time the Ti barrier metal layer 5 is exposed, the Ti and the dry etching gas, e.g., SF.sub.6 or CF.sub.4, reacts with each other, generating a fluoride TiF. As shown in FIG. 1B, the generated fluoride TiF is deposited on the interconnection material layer 6 of Blk-W, forming a film 9 of TiF which has an etching rate that is much lower than the etching rate of the Ti barrier metal layer 5.
The above difficulty experienced by the generation of the fluoride of Ti in the formation of the interconnection contact that is formed as the metal plug in the connecting hole defined in the inter-insulating layer also occurs in a structure as shown in FIGS. 2A and 2B of the accompanying drawings. In FIGS. 2A and 2B, an interconnection material layer 6 as of tungsten, molybdenum, polycrystalline Si, or the like is deposited on a surface 11 of a substrate 13 having a step 12 by anisotropic dry etching using a fluorine gas, with a barrier metal layer 5 disposed as a Ti base layer underneath the interconnection material layer 6. The interconnection material layer 6 is etched to a desired pattern extending across the step 12.
More specifically, as shown in FIG. 2A, the interconnection material layer 6 is deposited on the entire surface of the Ti barrier metal layer-5 which is composed of a lower barrier metal layer 5A of Ti and an upper barrier metal layer 5B of TiN on the entire surface of the surface 11 of the substrate 13 that has the step 12. To etch the interconnection material layer 6 to a predetermined pattern for thereby forming an interconnection of the same pattern, an etching resist 10 having that pattern is formed on the interconnection material layer 6, and then, using the etching resist 10 as a mask, the interconnection material layer 6 is etched by way of anisotropic dry etching using a fluorine gas, as shown in FIG. 2B. If the interconnection material layer 6 is deposited by CVD, for example, then it is deposited also on a vertical wall surface of the step 12, and the interconnection material layer 6 deposited thereon has a larger vertical thickness along the vertical wall surface of the step 12 in the etching direction.
Accordingly, even when the etching of the interconnection material layer 6 deposited on a horizontal surface and having a smaller vertical thickness is finished, exposing the barrier metal layer 5 therebeneath, the interconnection material layer 6 still remains unremoved as a remaining layer 6s (see FIG. 2B) on the vertical wall surface of the step 12. Thus, a film 9 of TiF is formed on the remaining layer 6s, and prevents the remaining layer 6s from being further etched away, so that an undesired interconnection material remains on the vertical wall surface of the step 12.
The remaining layer 6s causes a short circuit between interconnections on the substrate 13. One solution is to effect the etching process for a long period of time to etch away the film 9 which has a very low etching rate and the remaining interconnection material layer 6 disposed therebeneath, so that the unwanted remaining layer 6s will be eliminated from the step 12. If the etching process is prolonged, however, the interconnection material layer 6 on the horizontal surface will be overetched, resulting in unduly narrow interconnections. Therefore, high-density fine interconnection patterns for use in ULSI circuits, for example, cannot be formed highly reliably.